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[Other resource] altera_ram

Description: 本程序对如何使用altera系列芯片片上ram进行实例演示，采用Verilog HDL语言编写，并使用modelsim与quartus联合进行功能仿真。本原码是红色逻辑开发板的试验程序，值得一看。
Platform: | Size: 180374 | Author: panyouyu | Hits:

[Other resource] dul_ram(yk)

Description: 关于双口RAM的Verilog HDL源码
Platform: | Size: 3091 | Author: 123 | Hits:

[Applications] ZBT SRAM

Description: 用verilog HDL写的操作SRAM的源码-with Verilog HDL write operation SRAM FOSS
Platform: | Size: 6144 | Author: 刘波 | Hits:

[VHDL-FPGA-Verilog] verilog SDRAM core

Description: 我用过的verilog hdl写的SDRAM core源程序,经过测试应用-I used to write Verilog HDL source of SDRAM core, the test application
Platform: | Size: 27648 | Author: 于飞 | Hits:

[VHDL-FPGA-Verilog] sram

Description: sram 读写小程序，用verilog编写的，请各位高手指教-SRAM read and write small programs using Verilog prepared, please enlighten you master
Platform: | Size: 1024 | Author: kevin | Hits:

[Streaming Mpeg4] bit_intealeaver1

Description: verilog HDL语言实现dvb_t中的比特交织器源代码描述-verilog HDL language dvb_t the bit interleaver source code Description
Platform: | Size: 1024 | Author: wenjuner | Hits:

[VHDL-FPGA-Verilog] ddr_ctrl

Description: verilog hdl coding DDR sdram control for fpga -verilog hdl coding DDR sdram control for fpga
Platform: | Size: 27648 | Author: 王郁 | Hits:

[VHDL-FPGA-Verilog] altera_ram

Description: 本程序对如何使用altera系列芯片片上ram进行实例演示，采用Verilog HDL语言编写，并使用modelsim与quartus联合进行功能仿真。本原码是红色逻辑开发板的试验程序，值得一看。-This procedure of how to use the altera series chip-chip ram for example demonstration, using Verilog HDL language, and using ModelSim and Quartus functional simulation carried out jointly. Primitive code is red logic development board of the pilot program, worth a visit.
Platform: | Size: 180224 | Author: panyouyu | Hits:

[VHDL-FPGA-Verilog] dul_ram(yk)

Description: 关于双口RAM的Verilog HDL源码-On the dual-port RAM in Verilog HDL source
Platform: | Size: 3072 | Author: 123 | Hits:

[VHDL-FPGA-Verilog] DW8051_ALL

Description: 包中包括, DW8051完整的Verilog HDL代码 两本手册: DesignWare Library DW8051 MacroCell, Datasheet DesignWare DW8051 MacroCell Databook 三篇51论文: 基于IP 核的PSTN 短消息终端SoC 软硬件协同设计 Embedded TCP/ IP Chip Based on DW8051 Core 以8051为核的SOC中的万年历的设计 -DW8051 is designed by synopsys, and its instruction cycle is 4 clock, which lead to about 3 times faster than Intel 8051 with the same oscillator frequency. I writed ram, rom, some other perpherals such as DES, RNG, and its testbench, and it worked all right!
Platform: | Size: 1588224 | Author: myfingerhurt | Hits:

[VHDL-FPGA-Verilog] RAM_Examples

Description: Verilog hdl code for representing ram and rom "memory" using many methods
Platform: | Size: 5120 | Author: Muftah | Hits:

[VHDL-FPGA-Verilog] RAM

Description:
Platform: | Size: 573440 | Author: luoxs | Hits:

[VHDL-FPGA-Verilog] shift_regeister

Description: 用blockram实现移位寄存器，开发语言为verilog hdl-Shift register with blockram achieve the development language for the verilog hdl
Platform: | Size: 148480 | Author: 郭淮 | Hits:

[VHDL-FPGA-Verilog] DualPortRAM

Description: 此程序是Verilog HDL语言读写RAM的程序希望大家有用-This is Verilog HDL Promang
Platform: | Size: 1536000 | Author: 赵书俊 | Hits:

[VHDL-FPGA-Verilog] dual_RAM

Description: actel fusion startkit FPGA开发板试验例程，可实现2k8的双口ram，实现数据存储，缓冲。包含verilog HDL 语言源码-actel fusion startkit FPGA development board test routines, can be realized 2k8' s dual-port ram, achieving data storage, buffer. Language source code contains the verilog HDL
Platform: | Size: 608256 | Author: zhangyujun | Hits:

[VHDL-FPGA-Verilog] dp_ram

Description: 双口RAM的设计，采用Verilog HDL语言编写。-Dual-port RAM design, using Verilog HDL language.
Platform: | Size: 2048 | Author: 信仰 | Hits:

[VHDL-FPGA-Verilog] idt71v416s10

Description: code for ram in verilog hdl
Platform: | Size: 2048 | Author: Oleg | Hits:

[VHDL-FPGA-Verilog] NET2

Description: This file with the wavelet transf Mallat implementation of wavelet Verilog hdl code modules for radi Modelsim 6.6 crack, can be used f A written using Verilog DDR2 cont Simple CPU VHDL implementation an Dual-port RAM design, using Veril Verilog language, a hardware-base FPGA embedded project combat, Man Application FPGA, FPGA-chip hardw Mallat implementation of wavelet Layer of one-dimensional wavelet
Platform: | Size: 1852416 | Author: sansfroid | Hits:

[VHDL-FPGA-Verilog] ram rom verilog

Description: ram rom verilog hdl verilog
Platform: | Size: 5618 | Author: mamine2ia | Hits:

[VHDL-FPGA-Verilog] Verilog的135个经典设计实例

Description: Verilog的135个经典设计实例，部分摘录如下：【例 9.23】可变模加法/减法计数器【例 11.7】自动售饮料机【例 11.6】“梁祝”乐曲演奏电路【例 11.5】交通灯控制器【例 11.2】4 位数字频率计控制模块【例 11.1】数字跑表【例 9.26】256×16 RAM 块【例 9.27】4 位串并转换器【例 11.8】多功能数字钟【例 11.9】电话计费器程序【例 12.13】CRC 编码【例 12.12】（7，4）循环码纠错译码器【例 12.10】（7，4）线性分组码译码器【例 12.7】11 阶FIR 数字滤波器。。。。。。。(135 classic examples of Verilog design)
Platform: | Size: 167936 | Author: 三棵树机务段 | Hits:
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